Semiconductor package and method for fabricating the same
US6369454B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Dec 14, 1999 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Dec 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method of making the package are disclosed. The package includes a semiconductor chip having first surface with a conductive pad thereon. A first end of a bond wire is connected to each of the pads. Encapsulant covers the fist surface of the chip, the pads, and the bond wires, and forms side surfaces of the package. A second end of the bond wires is exposed at a side surface of the package. Making the package includes providing a wafer including a plurality of semiconductor chip units. Each chip unit has a plurality of conductive pads at a first surface of the wafer. A bond wire is electrically connected between each pad of each semiconductor chip unit and a pad of at least one adjacent semiconductor chip unit of the wafer. An encapsulant is applied onto the first surface of the wafer so as to completely cover the bond wires and pads of the semiconductor units. The encapsulated wafer is separated between adjacent semiconductor chip units so as to sever the bond wires and form individual packages each having side surfaces formed of the encapsulant. A severed end of each bond wire is exposed at a side surface of the respective package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.