High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes

US6370668B1 · kind B1 · utility

Assignee

• Rambus Inc. · US

Inventors

• Billy Wayne Garrett, Jr. · Mountain View, US
• Frederick A. Ware · Los Altos Hills, US
• Craig E. Hampel · San Jose, US
• Richard M. Barth · Palo Alto, US
• Don Stark · Palo Alto, US
• Abhijit M. Abhyankar · Sunnyvale, US
• Catherine Chen · Cupertino, US
• Thomas J. Sheffler · San Francisco, US
• Ely Tsern · Los Altos, US
• Steven C. Woo · Saratoga, US

Key dates

• Filing date: Sep 14, 1999
• Grant date: Apr 9, 2002
• Expiry date: Sep 14, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/1072
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.