Method of forming a capacitor container electrode and method of patterning a metal layer by selectively silicizing the electrode or metal layer and removing the silicized portion
US6372574B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jun 2, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/957
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of patterning a metal layer includes masking a first portion of a metal layer while leaving a second portion of the metal layer unmasked over a substrate. With the masking in place, the second portion is reacted with silicon to form a metal silicide from the metal layer. The metal silicide is removed from the substrate while substantially leaving the first portion on the substrate. The masking is removed from the substrate. A method of patterning a metal layer includes depositing and patterning a silicon comprising layer over a substrate. A metal layer is formed over the patterned silicon comprising layer, and includes a portion extending to elevationally inward of the metal layer. Metal of the metal layer is reacted with silicon of the silicon layer to form a metal silicide and leave at least some of the portion unreacted. The metal silicide is removed from the substrate while substantially leaving the unreacted portion of the metal layer on the substrate. These and other implementations can be used to form capacitor container electrodes and other circuit devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.