Method for making transistor having reduced series resistance
US6372590B1 · kind B1 · utility
12Cited by
29References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1997 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Oct 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection with the implantation of a conventional n-type dopant (e.g. arsenic or phosphorus), results in a transistor having low series resistance, reduced hot carrier effects and no significant increase in source/drain extension overlap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.