Method and apparatus for multiple row activation in memory devices
US6373761B1 · kind B1 · utility
17Cited by
22References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Sep 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device test circuit and method are described. These operate to maintain a local phase signal active over multiple row activate commands. As a result, an arbitrary number of word lines may be activated together, in an arbitrary order and in arbitrary locations, in response to user-programmable instructions. This allows test sequences to be tailored after the memory device has been designed and can greatly reduce testing times for memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.