Error checking of simulated printed images with process window effects included
US6373975B1 · kind B1 · utility
54Cited by
12References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jan 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.