Data processing apparatus with a cache controlling device
US6374334B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1997 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Oct 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus temporarily stores data to a cache write buffer and then stores the data in a cache storing device. The cache storage device performs a data storage operation with precedence over another operation even if a store instruction contends with a read instruction for accessing the cache storing device. A storage request low signal, sent from a cache write buffer controlling device to a cache controlling device, allows a read request to have precedence over a store instruction even when there is data stored in the cache write buffer waiting to be transferred to the cache storing device in response to the store instruction. However, when the read instruction contends with the store instruction and a state transition signal, such as an instruction cancellation signal generated from an instruction controlling device, is detected, the cache write buffer controlling device changes the output signal to a storage request high signal that causes the storage operation to have precedence over the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.