Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test
US6374376B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 1998 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Sep 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.