Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip
US6374394B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Oct 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; onc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.