Annealed porous silicon with epitaxial layer for SOI
US6376285B1 · kind B1 · utility
67Cited by
2References
8Claims
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Key dates
| Filing date | May 20, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | May 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.