Semiconductor memory device and a method for fabricating the same
US6376304B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed; therefore, a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied. Besides, interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, the filling up of the holes with metal and the like are unnecessary and, as a result, reliability of the process is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.