Formation of non-volatile memory device comprised of an array of vertical field effect transistor structures
US6376312B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Mar 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
For fabrication of a vertical field effect transistor structure for each of an array of flash memory cells for a non-volatile memory device, an opening is etched though top and bottom layers of doped insulating material and a layer of dummy material formed between the bottom and top layers of doped insulating material. The opening is filled with a semiconductor material to form a semiconductor fill. The layer of dummy material is etched away such that a channel region of the semiconductor fill is exposed. A tunnel gate dielectric is formed on the channel region of the vertical field effect transistor. A floating gate electrode material is deposited to abut the tunnel gate dielectric. The tunnel gate dielectric and the floating gate electrode material are disposed on a plurality of planes of the channel region of the vertical field effect transistor. Dopant diffuses from the top and bottom layers of doped insulating material into the semiconductor fill to form drain and source extension junctions. A control gate dielectric material and a control gate electrode material are deposited on any exposed surfaces of the floating gate electrode material. The control gate electrode material …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.