Variable porosity porous silicon isolation
US6376859B1 · kind B1 · utility
13Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jul 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while greater porosity in other portions of the layer increases circuit isolation and provides stress relief between layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.