Methods for eliminating metal corrosion by FSG
US6380066B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating metal plugs within via openings comprising the following steps. A semiconductor substrate having an overlying metal layer and oxide hard masks overlying the metal layer is provided. The oxide hard masks are used to etch the metal layer to form metal lines separated by metal line openings. An oxide liner is formed over the etched structure. A layer of FSG is deposited over the oxide liner. The FSG layer is then planarized to remove: the excess of the FSG layer from the etched structure; and the portions of the oxide liner over the oxide hard masks to form FSG blocks within the metal line openings. A cap layer is formed over the planarized structure. The cap layer and hard masks are then planarized to form via openings exposing the metal lines. Planarized metal plugs are then within the via openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.