Alex See
55Patents
15h-index
76Co-inventors
83Inventor score
Filing activity: Sep 9, 1999 → Dec 18, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6303418A | Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer | Electricity | 316 | Expired |
| US6261935A | Method of forming contact to polysilicon gate for MOS devices | Electricity | 194 | Expired |
| US6348385B1 | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant | Electricity | 65 | Expired |
| US6897118B1 | Method of multiple pulse laser annealing to activate ultra-shallow junctions | Electricity | 60 | Expired |
| US6387747B1 | Method to fabricate RF inductors with minimum area | Electricity | 35 | Expired |
| US6391731B1 | Activating source and drain junctions and extensions using a single laser anneal | Electricity | 29 | Expired |
| US6355563B1 | Versatile copper-wiring layout design with low-k dielectric integration | Electricity | 27 | Expired |
| US6365446B1 | Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process | Electricity | 25 | Expired |
| US6281082A | Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill | Electricity | 23 | Expired |
| US6335253B1 | Method to form MOS transistors with shallow junctions using laser annealing | Electricity | 23 | Expired |
| US6319767A | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique | Electricity | 21 | Expired |
| US7091092B2 | Process flow for a performance enhanced MOSFET with self-aligned, recessed channel | Electricity | 20 | Expired |
| US6613652B2 | Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance | Electricity | 20 | Expired |
| US6391720B1 | Process flow for a performance enhanced MOSFET with self-aligned, recessed channel | Electricity | 19 | Expired |
| US6650220B2 | Parallel spiral stacked inductor on semiconductor material | Emerging Cross-Sectional Technologies | 15 | Expired |
| US6899857B2 | Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique | Electricity | 14 | Expired |
| US6475875B1 | Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer | Electricity | 13 | Expired |
| US6624489B2 | Formation of silicided shallow junctions using implant through metal technology and laser annealing process | Electricity | 11 | Expired |
| US8518775B2 | Integration of eNVM, RMG, and HKMG modules | Electricity | 9 | Active |
| US6380066B1 | Methods for eliminating metal corrosion by FSG | Electricity | 8 | Expired |
| US6432797B1 | Simplified method to reduce or eliminate STI oxide divots | Electricity | 8 | Expired |
| US6468880B1 | Method for fabricating complementary silicon on insulator devices using wafer bonding | Emerging Cross-Sectional Technologies | 8 | Expired |
| US7112499B2 | Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal | Electricity | 8 | Expired |
| US6905964B2 | Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer | Electricity | 7 | Expired |
| US6436833B1 | Method for pre-STI-CMP planarization using poly-si thermal oxidation | Electricity | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.