Deposition of various base layers for selective layer growth in semiconductor production

US6380074B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Markus Kirchhoff · Radeberg, DE
• Hans-Peter Sperlich · Dresden, DE
• Uwe Schilling · Dresden, DE
• Zvonimir Gabric · Zorneding, DE
• Oswald Spindler · Vaterstetten, DE
• Stephan Wege · Osterburken, DE
• Hans Glawischnig · Dresden, DE

Key dates

• Filing date: Sep 18, 2000
• Grant date: Apr 30, 2002
• Expiry date: Sep 18, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.