Apparatus and methods of packaging and testing die
US6380631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | May 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die. In an alternate embodiment, the packaging substrate comprises an electrically conductive substrate and an electrically insulative material is formed between the conductive leads and the pac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.