High speed, low cost BICMOS process using profile engineering

US6383855B1 · kind B1 · utility

Assignee

• Institute of Microelectronics · SG

Inventors

• Minghui Gao · Singapore, SG
• Haijun Zhao · Beijing, CN
• Abhijit Bandyopadhyay · San Jose, US
• Pang Dow Foo · Singapore, SG

Key dates

• Filing date: Nov 4, 1998
• Grant date: May 7, 2002
• Expiry date: Nov 4, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and fT may be increased to 20 GHz or higher.