Method for fabricating a capacitor in a semiconductor device
US6383865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Jun 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a capacitor of a semiconductor device, comprising the steps of forming a seed layer over a semiconductor substrate, and forming multiple oxide layers on the seed layer, wherein wet etching of the multiple oxide layers decreases as the layers go up. A first opening is formed by exposing the seed layer by selectively dry etching the multiple oxide layer. A second opening is formed by wet etching the lateral surface of the first opening where the width of the first opening is expanded, wherein the lower part of the second opening is larger than the upper part. A bottom electrode is formed on the seed layer exposed at the bottom of the second opening, whereby the bottom electrode has an identical shape with the second opening, and the bottom electrode is formed with the ECD (Electro-Chemical Deposition) technique. The seed layer is exposed by removing the multiple oxide layer and then the exposed seed layer is removed. A dielectric layer is formed on the bottom electrode and a top electrode is formed on the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.