Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption
US6383906B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Aug 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming ultra shallow junctions in a semiconductor wafer uses disposable spacers and a silicon cap layer to achieve ultra-low low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of a semiconductor device. Silicon nitride disposable spacers are formed over the metal layer in the region of the sidewall spacers previously formed on the sidewalls of the gate. A silicon cap layer is deposited over the metal layer and the disposable spacers. Rapid thermal annealing is performed to form the high-ohmic phase of the salicide, with the disposable spacers preventing interaction and between the cobalt and the silicon in the area between the gate and the source/drain junctions along the sidewall spacers. The silicon cap layer provides a source of silicon for consumption during the first phase of salicide formation, reducing the amount of silicon of the source/drain junctions that is consumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.