Integrated circuit structure including three-dimensional memory array
US6385074B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Dec 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.