Circuit and method for maintaining order of memory access requests initiated by devices in a multiprocessor system
US6385705B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Dec 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access trans…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.