Using a timing-look-up-table and page timers to determine the time between two consecutive memory accesses
US6385708B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1999 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Nov 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the present invention, a scheduler that uses a timing-look-up-table and page timers to determine the time between two consecutive memory accesses is described. The scheduler for scheduling a plurality of commands to an associated memory, the memory comprising a plurality of M memory banks and a plurality of N memory pages includes restriction circuitry for determining an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank and reordering circuitry for determining an order in which the commands should be transmitted to the associated memory with reference to the earliest issue time associated with each command and a data occurrence time associated with selected ones of the commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.