Circuit and method for incrementally selecting word lines
US6388946B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | May 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.