Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system
US6389526B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1999 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Aug 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.