Method for fabricating an array of ultra-small pores for chalcogenide memory cells

US6391688B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Fernando Gonzalez · Boise, US
• Raymond A. Turi · Boise, US

Key dates

• Filing date: Oct 23, 2000
• Grant date: May 21, 2002
• Expiry date: Oct 23, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared. The pores thus defined are further equally spaced from adjacent pores by a spacing ranging from approximately 0.25 to 0.5 microns. The pores thus defined may then be used to fabricate an array of chalcogenide memory cells.