Process for forming gate conductors
US6391753B1 · kind B1 · utility
203Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jun 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.