Method of fabricating local interconnect
US6391760B1 · kind B1 · utility
0Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a local interconnect is provided. A semiconductor is provided. An isolation structure, a transistor and a conductive layer are formed on the substrate. A dielectric layer with an opening is formed over the substrate. A part of the dielectric layer is removed by a photolithography and etching process to form a via opening to expose a part of the gate of the transistor or a part of the conductive layer. A conformal barrier layer is formed in the via opening and overflows the dielectric layer. A conductive plug is formed in the via opening. The barrier layer is patterned to form a local interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.