Dual silicide process to reduce gate resistance
US6391767B1 · kind B1 · utility
18Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Feb 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0213
Abstract
A method of reducing the gate resistance in a semiconductor device forms a gate in the semiconductor device followed by the creation of a silicide region on top of the gate. During the initial formation of the silicide region on the gate, formation of silicide on source/drain areas of the semiconductor device is prevented by a shielding material. The shielding material is then removed and additional silicide is created, forming silicide regions on the source/drains and increasing the thickness of the silicide over the gate, thereby lowering the gate resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.