Integrated structure for reduced leakage and improved fill-factor in CMOS pixel
US6392263B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
Abstract
A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor.In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.