Semiconductor device with self refresh test mode
US6392948B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jul 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. The self refresh test mode controller provides at least one or more of the following four functions: (1) the ability to control internal signals while in self refresh test mode; (2) the ability to monitor internal signals while in self refresh test mode; (3) the ability to put in a programmable delay, change the delay, or change internal timing while in self refresh test mode (add delay or make delay programmable, adjustable); (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while the column address is frozen). As examples, the following signals may be analyzed and acted upon by the self refresh test mode controller, or transmitted through the self refresh test mode controller t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.