Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products
US6395568B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jul 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for bond pad crater jeopardy identification in integrated circuits, and apparatus which performs the method. The gate or gates of a transistor or transistors of an ESD device are formed under each bond pad in the integrated circuit device. Connected to the transistor is circuitry for determimg the electrical, and hence mechanical, integrity of the transistor. A reduction in current through the transistor, by reason of microcrack formation in the several layers under the transistor causing a gate or gates of the transistor to crack and fail, may detected, Location of at least a portion of the ESD device, for example the above transistor, reduces overall chip area by increasing device density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.