Controlling packaging encapsulant leakage
US6395579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2001 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Feb 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.