Method of fabricating a MOS transistor in an embedded memory
US6395596B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2001 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Mar 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
Abstract
The present invention provides a method of fabricating a MOS transistor in an embedded memory. A first dielectric layer, an undoped polysilicon layer, and a second dielectric layer are formed on the periphery circuits area. Next, the undoped polysilicon layer in the memory array area is doped, followed by removal of the second dielectric layer in the memory array area. Then, a silicide layer and a protective layer are formed and portions of the memory array area are etched to form gates. LDDs in each MOS transistor in the memory array area are formed. Next, LDDs in each MOS transistor in the periphery circuits area are formed. A portion of the silicon nitride layer and the silicon oxide layer in the periphery circuits area form a spacer on either side of each gate in the periphery circuits area. Finally, a source and drain (S/D) are formed in the periphery circuits area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.