Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit
US6395611B1 · kind B1 · utility
12Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1999 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Nov 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.