Array organization for high-performance memory devices
US6396728B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jul 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices including blocks of memory cells arranged in columns, with each column of memory cells coupled to a main bit line, are organized for high-speed access and tight packing. Such memory devices include sector bit lines having multiple main bit lines selectively coupled to each sector bit line, with each sector bit line extending to main bit lines in each memory block of a memory sector. Sector bit lines are coupled to sensing devices and the output of each sensing device is selectively coupled to a global bit line, with each global bit line selectively coupled to more than one sensing device. The global bit lines are multiplexed and input to helper flip-flops for output to the data output register of the memory device. Various embodiments include non-volatile, and, particularly, synchronous non-volatile memory devices having multiple banks containing multiple sectors of such memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.