Integrated memory with redundancy and method for repairing an integrated memory
US6396750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jun 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/702
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.