Process of manufacturing semiconductor integrated circuit device having an amorphous silicon gate
US6399453B2 · kind B2 · utility
6Cited by
2References
36Claims
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Key dates
| Filing date | Jun 27, 2001 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Jun 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Desired operating characteristics are obtained from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.