Method and system for re-routing interconnects within an integrated circuit design having blockages and bays
US6401234B1 · kind B1 · utility
95Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for re-routing interconnects within an integrated circuit design having blockages and bays is disclosed. A net within the integrated circuit design is initially decomposed into multiple two-paths. The net includes interconnects previously routed by utilizing a Steiner tree routing algorithm. Next, a cost associated with each of the two-paths is calculated. A two-path having a a high cost is subsequently selected and re-routed with a lower cost two-path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.