Method for determining on-chip sheet resistivity
US6403389B1 · kind B1 · utility
23Cited by
22References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Aug 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method measures a resistance in a test structure to determine the sheet resistivity of a test structure. In one embodiment, a family of test structures is provided to determine the effective sheet resistivity of a conductor as a function of its width. The method is applicable to conductors in manufacturing processes in which “slots” or “islands” are created in the conductor to prevent dishing during chemical-mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.