Method for in-situ fabrication of a landing via and a strip contact in an embedded memory
US6403417B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2001 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Mar 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method to integrate the process of manufacturing an embedded memory and the sequential process of forming a landing via and a strip contact in the embedded memory. The method involves first defining a memory array region and a periphery circuit region on the surface of a silicon substrate of a semiconductor wafer. Next, a plurality of gates and lightly doped drains are separately formed in the memory array region and the periphery circuit region. A silicon nitride layer then covers the surface of each gate in the memory array region, and forms a spacer on either side of each gate in the periphery circuit region. Then, a dielectric layer is formed on the surface of the semiconductor wafer, and a landing via hole and a strip contact hole are separately formed in the dielectric layer in the memory array region and the periphery circuit region, respectively. Finally, each hole is filled with a conductive layer to form in-situ each landing via and strip contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.