Fabrication process of semiconductor integrated circuit device
US6403459B1 · kind B1 · utility
12Cited by
17References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/11
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.