Method and apparatus for run-to-run controlling of overlay registration
US6405096B1 · kind B1 · utility
64Cited by
8References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Aug 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a method and apparatus for correction of overlay control errors. Semiconductor devices are processed based upon control input parameters. The processed semiconductor devices are examined in a review station. The control input parameters are modified in response to the examination of the processed semiconductor devices. New control input parameters are implemented for a subsequent run of the semiconductor device processing step based upon the modification of the control input parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.