Multiprocessor system bus protocol for O state memory-consistent data
US6405290B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1999 |
| Grant date | Jun 11, 2002 |
| Priority date | — |
| Expiry date | Jun 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes an interconnect, a system memory and a number of snoopers coupled to the interconnect, and response logic. In response to a requesting snooper issuing a data request on the interconnect specifying a memory address, the snoopers provide snoop responses. The response logic compiles the snoop responses to obtain a combined response including an indication of a demand-source snooper that will source requested data associated with the memory address to the requesting snooper and an indication of whether additional non-requested data will be supplied to the requesting snooper. This combined response is then transmitted to the snoopers on the interconnect to direct the provision of the requested data, and possibly unrequested prefetch data, to the requesting snooper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.