Wafer level production of chip size semiconductor packages
US6406934B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2000 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Sep 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a manufacturing process for making chip-size semi-conductor packages (“CSPs”) at the wafer-level without the added size, cost, and complexity of substrates in the packages or the need to overmold them with plastic. One embodiment of the method includes the provision of a semiconductor wafer with opposite top and bottom surfaces and a plurality of dies integrally defined therein. Each die has an electronic device formed in a top surface thereof, and one or more electrically conductive vias extending therethrough that electrically connect the electronic device to the bottom surface of the die. The openings for the vias are formed ablatively with a laser and plated through with a conductive material. In a BGA form of the CSP, the vias connects the electronic device to lands on the bottom surface of the die. The lands may each have a bump of a conductive metal, e.g., solder, attached to it that functions as an input-output terminal of the CSP. When fabrication of the wafer is complete, the finished packages are singulated from the wafer using conventional wafer cutting techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.