Process for fabricating an ONO structure having a silicon-rich silicon nitride layer

US6406960B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Dawn Hopper · San Jose, US
• David K. Foote · San Jose, US
• Bharath Rangarajan · Santa Clara, US
• Arvind Halliyal · Cupertino, US

Key dates

• Filing date: Oct 25, 1999
• Grant date: Jun 18, 2002
• Expiry date: Oct 25, 2019

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/954

Abstract

A process for fabricating an ONO layer in a non-volatile memory device including the steps of forming a first silicon oxide layer, a silicon-rich silicon nitride layer and a second silicon oxide layer. The silicon-rich silicon nitride layer is formed by either a PECVD process, an LPCVD, or an RTCVD process. The silicon-rich silicon nitride layer effectively holds electrical charge making the ONO layer particularly useful as a floating gate electrode in a two-bit EEPROM device.