Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data
US6408362B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Jun 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit and to the distributed memory. The cache includes a congruence class containing a plurality of cache lines and a plurality of latency indicators that each indicate an access latency to the distributed memory for a respective one of the cache lines. The cache further includes a cache controller that selects a cache line in the congruence class as a castout victim in response to the access latencies indicated by the plurality of latency indicators. In one preferred embodiment, the cache controller preferentially selects as castout victims cache lines having relatively short access latencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.