Apparatus and method for executing floating-point store instructions in a microprocessor
US6408379B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Jun 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4991
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.