Method and structure for testing embedded analog/mixed-signal cores in system-on-a-chip
US6408412B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 1999 |
| Grant date | Jun 18, 2002 |
| Priority date | — |
| Expiry date | Sep 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3167
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing an embedded analog core in an integrated circuit chip having a microprocessor core and a memory core. The method includes the steps of providing a test register in the integrated circuit chip between the microprocessor core and an analog core to be tested, testing the microprocessor core and the memory core, using an assembly language test program running on the microprocessor core to generate a test pattern by the microprocessor core, applying the test pattern to the analog core by the microprocessor core and evaluating the response of the analog core either by the microprocessor core or a test system provided outside of the integrated circuit chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.