Substrate cooling system
US6408537B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 2000 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | May 30, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for staging or cooling a substrate between high temperature thermal processing steps. In the disclosed embodiment, one or more cooling stations are located off-line within a wafer handling chamber, outside the thermal processing chamber. After thermal processing, a hot wafer can be loaded on to one station, where the wafer is subjected to forced convection cooling. In particular, the wafer is subjected to cooling gas from above and below through perforated upper and lower showerhead assemblies. The wafer can thus be cooled rapidly on a station while other wafers are transferred into and out of the processing chamber, Desirably, the wafer is cooled on the station to a point at which it can be handled by a low temperature wafer handler and stored in a low temperature cassette.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.